I'm nearing the end of my senior year (graduation May 14th) and I have been working hard to get my groups senior design project up and running. We made a couple of good decisions and a couple of bad decisions. I failed to recognize some situations and I forced certain other situations. Number one bad decision was the work load I took on. I ended up working 232 hrs in total and over 70 hours in the last week. My biggest flaw was not trying to teach my group what I did and have them work on my parts as well. The most glaring example of this is the PCB and schematics we created. I use gEDA to do all of my electrical design. While gEDA is not the simplest program to use, I took on the posistion because I had the most experience doing schematic capture and layout. This task should have been handed off because what is more important is the Linux based datalogging system. I wrote the datalogger in a total of 12 hrs, it is the most awful, ugly and offensive program I have ever written, however this program has the most potential to be globally useful and a program which others could use to avoid the problems we faced. I wish I was able to hand of the schematic capture and layout to other in order to allow me the opportunity to work on the datalogging program. Who knows maybe I will get a chance to rewrite it but until then I hope to never be associated with that program.
A blog of interesting technical advances.